Advances in the use of the Internet have increased the demands upon Internet servers to provide multimedia data files. These data files include digital representations of text, sound, photographs, animation, and video which are stored on servers called media-servers. As the Internet has evolved, the speed with which multimedia files must be transferred from media servers to Internet users has increased. This has thus resulted in the need for media servers that can quickly receive requests for data and respond with data transmission such that the media server does not become a bottleneck to the flow of data to Internet users.
Media servers are electrically-powered systems that typically include a plurality of storage devices capable of storing and retrieving data, i.e., disk drives, that are usually of the same type and capacity. The plurality of storage devices are under the control of a computer processor referred to as a storage controller. In many applications, the storage controller is a Redundant Array of Inexpensive Drives (RAID) controller, a storage controller which implements a RAID configuration. The basic RAID configuration is disclosed in U.S. Pat. No. 4,870,643, entitled “PARALLEL DRIVE ARRAY STORAGE SYSTEM,” the content of which is incorporated herein by reference.
In general terms, the RAID controller interprets and controls data written to and read from an array of disk drives. Data is stored in the drives of the array in a “striped” arrangement. Each stripe includes a plurality of successive data bytes that are stored in the same numerical location of the drives. One of the drives may be used to store a check (parity) byte for each stripe such that the data for a storage device that has malfunctioned or is temporarily removed from service may be reconstructed, as is described in further detail in U.S. Pat. No. 5,191,584, entitled “MASS STORAGE ARRAY WITH EFFICIENT PARITY CALCULATION,” the content of which is incorporated herein by reference.
One drawback with current storage controllers including RAID controllers is that they are implemented with multiple semiconductor chips. In a typical approach, an off-the-shelf control protocol chip is purchased together with a memory buffer chip and a parity engine chip, and combined together to create a storage controller. The various chips are interconnected via pins and a local bus to allow communication between the chips. The physical separation between the chips and their interconnection via physical pins and the bus interface generally results in processing and transmission delays, increased power consumption, and increased space consumption. Media servers having large power consuming storage controllers generally require additional cooling systems, power supplies, and associated monitoring systems. This results in further power consumption by the media server and increased manufacturing costs in the purchase and installation of multiple components.
For a typical RAID storage controller, its implementation via multiple chips may also cause delays in the detection and reconstruction of data of a failed disk drive. One distinguishing feature of media servers is the requirement to deliver data intended for real time use. One example of such a data is video data, which in the U.S. must typically be displayed at a fixed frame rate of usually 29.97 frames per second. In this environment, delays that may be of no consequence to a general computer application are considered failures by the media server. Such delays, however, may be common for disk drive mechanisms. Accordingly, it is desirable for the media server to efficiently identify and recover from delays caused by the disk drive mechanisms in order to prevent data transmission interruptions.
FIG. 1A is a schematic block diagram of a conventional RAID storage controller system that detects a failed disk drive and provides data reconstruction functionality. The system includes a plurality of disk drives 102, a protocol chip 100 associated with each disk drive, a memory buffer chip 104, a microprocessor chip 106, and a parity engine chip 108, which are all interconnected to each other and to a host computer 110 via a data communications bus 112. The plurality of disk drives 102 forms a RAID disk drive array. The microprocessor chip 106 determines particular locations of the disk drives for reading and writing a data stripe based on requests received from the host computer 110. The memory buffer chip 104 stores data read from the disk drives, and data to be written into the disk drives. The parity engine chip 108 includes logic for calculating check bytes via exclusive OR (XOR) functions. The check bytes are used in recreating data in a particular position of a failed disk drive in conjunction with the data stripe stored in the same position of other non-failed disk drives.
The reconstruction process of a failed disk drive in the storage controller system of FIG. 1A demands multiple transfers of data across the data communications bus 112 for accessing various chip components involved in the reconstruction process. In a typical scenario, four or more trips across the bus may be required. In this regard, a data stripe of the non-failed disk drives is read and transferred over the bus to the memory buffer 104. The data stripe is transferred again over the bus to the separate parity engine chip 108. The parity engine chip utilizes the data stripe to reconstruct the failed portion of the failed disk drive, and utilizes the bus to transfer the reconstructed stripe to the memory buffer 104. The memory buffer 104 then transmits the reconstructed stripe over the bus for writing the stripe to the disk drives including the failed disk drive. The reconstructed stripe may also be transmitted to the requesting host 110. The process continues until all the data stripes of the non-failed disk drives are read and the failed disk drive has been fully reconstructed.
FIG. 1B is a block diagram of an alternate RAID storage controller system that may also be conventional in the art. Unlike the system of FIG. 1A, the alternate system of FIG. 1B requires a less number of data transfers across the data communications bus 112 since data for a failed disk drive is reconstructed by the parity engine chip 108 prior to an initial storage in the memory buffer 104. Thus, in a typical scenario, a data stripe in the non-failed disk drives is read and transferred over the bus to the parity engine chip 108 which reconstructs the failed portion of the failed disk drive. The reconstructed stripe is transferred over the bus 112 to the memory buffer 104. The memory buffer 104 then transmits the reconstructed stripe over the bus for writing the stripe to the disk drives.
FIG. 1C is a timing diagram of the data reconstruction process that may be executed by the alternate RAID storage controller system of FIG. 1B. Each T0, T1, and T2 is assumed to be a period needed for a disk to complete a revolution. Each D0, D1, and D2 is assumed to be a disk drive in a three disk-drive array. In the illustrated example, it is assumed that D2 is the failed disk drive.
At T0, a read is performed in parallel on both non-failed disk drives D0 and D1 for reading a data stripe. At T1, the failed data is reconstructed and transmitted to the memory buffer under the control of the microprocessor. At T1, however, the disk drives have completed a revolution and are in position for performing another read or write. Nonetheless, the disk drive remain idle due to the delays in transmitting the reconstructed stripe to a memory buffer on a separate chip prior to being written to the disk drives. At T2, the microprocessor transmits the reconstructed stripe from the memory buffer to the drives for parallel writing of the data stripe.
In the storage controller system illustrated in FIG. 1A, the idle time for the non-failed disk drives is greater since the read data stripe is first stored in the memory buffer, then transmitted to the parity engine chip for reconstruction, and back to the memory buffer for storage, before the reconstructed data may be written or another data stripe to be reconstructed may be read. It is important, however, that the reading and writing of data stripes during reconstruction of a data drive be performed with minimal delays to avoid the risk of a failure of a second disk drive while a first failed disk drive is being reconstructed. Accordingly, what is desired is a storage controller system that minimizes the time needed for reconstructing a failed disk drive.
Another disadvantage with current media servers is that the housing of personal computers typically utilized as part of the media servers offer a limited amount of space for storage devices. Thus, the plurality of disk drives used in conjunction with a storage controller are often too large to fit within the housing of a personal computer. As a result, current media servers have separate housings for the plurality of storage devices, thus, imposing the requirement for extra floor space and external cabling for interconnection of the plurality of disk drives and storage controller with the other components of the media server. One disadvantage associated with current media servers is the common failure resulting from inadvertent cable disconnection.
Media servers also include data switches which route data from the plurality of storage devices and storage controller to interface processors which format the data for transmission to Internet users. Current data switches use high level protocols, agreed-upon formats for transmitting data between devices, such as Fibre Channel, Gigabit Ethernet, or ATM (asynchronous transfer mode). These high level protocols have the added disadvantage of requiring extensive, expensive electronics or very high speed processors which are difficult to use in very high bandwidth due to their complexity. Furthermore, the digital logic of current media server data switches is embodied in electronic circuitry having multiple electronic chips. As stated previously for storage controllers, having multiple electronic components results in slower speed and larger power consumption.
Another disadvantage associated with current media servers is the slow speed associated with the transmission of data from interface processors to Internet user's remote computer. In current media servers, the interface processor has to both generate packet headers for data transmitted from the media server and remove packet headers from data being stored on the media server. The constant flow of data back and forth across the interface processors internal data bus slows the data transfer speed and reduces the efficiency of the interface processor.
Current media servers also have the added disadvantage of not permitting removal of the electronic components, electronic circuit boards, and storage devices from the media server while the media server is electrically powered, commonly known as hot swappability. Permitting hot swappability of the electronic components, electronic circuit boards, and storage devices facilitates the removal and replacement of faulty components without interruption of media server service to Internet users.
Accordingly, it should be appreciated that there is a need for a cableless media server that encloses all of its components, including the plurality of storage devices, within one housing. Also, there is a need for a storage controller and a data switch which each implement their associated digital logic on a single electronic chip. Furthermore, there is the need for a media server having a data switch which implements a low level protocol. In addition, a need exists for a media server that offers increased data transmission speed from the data switch to the Internet user. Moreover, there is a need for a media server in which the electronic components, electronic circuit boards, and storage devices are hot swappable.